“pseudo-random permutation”

An Analog-to-Information VGA Image Sensor Architecture for Support Vector Machine on Compressive Measurements

Abstract: This work presents a compact VGA (480 × 640) CMOS Image Sensor (CIS) architecture with dedicated end-of-column Compressive Sensing (CS) scheme allowing embedded object recognition. The architecture takes advantage of a low-footprint pseudo-random data mixing circuit and a first order incremental Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) to extract compressed features.