A Low-Memory Compressive Image Sensor Architecture for Embedded Object Recognition

Proceedings of MWSCAS 2018

Abstract: This work presents a compact image sensor architecture with end-of-column digital processing dedicated to perform embedded object recognition. The architecture takes advantage of a Compressed Sensing (CS) scheme to extract compressed features and to reduce data dimensionality based on a low footprint pseudo random data mixing. Taking advantage of the intrinsic property of a first order incremental Sigma-Delta (Sigma Delta) Analog to Digital Converter (ADC), an optimized Digital Signal Processing (DSP) is proposed to implement the affine projection applied by a linear Support Vector Machine (SVM) classifier. This architecture allows to achieve an acceptable object recognition accuracy of 80% on the Georgia Tech face database (50 classes). On the other hand, the signal independent dimensionality reduction performed by our dedicated sensing scheme (1/512) allows to dramatically reduce memory requirements (125 kbits) related -in our case- to the ex-situ learned affine function of the linear SVM.